1. Technical Field
The present invention is directed generally toward a method and apparatus for managing memory within an integrated circuit device, and more particularly is directed toward a memory management unit that provides run-time swap support for an integrated controller while maintaining a small physical footprint size.
2. Description of the Related Art
Certain types of input/output (I/O) devices for a computer system require a microprocessor, microcontroller or other type of device controller such as a dedicated state machine to facilitate co-action between the I/O device(s) and another controller or processor within the computer system. Such auxiliary device controllers off-load processing and control requirements that would otherwise be required of the other system processor (such as a primary central processing unit or CPU) in performing an I/O operation with a particular I/O device. Hard disk drives, either singularly or configured in a group such as a RAID (redundant array of inexpensive disks) group, are one such type of I/O device that benefits from having an I/O device controller to facilitate data transfer between the main system processor and the disk drive(s). The device controller is able to provide support for the particular type of interface or protocol that the I/O device(s) use to communicate with other computing devices such as a computer system. For example, serial-attached SCSI (SAS) is one type of interface/protocol that is used to communicate with a disk drive. In such an environment, a system motherboard containing a traditional system microprocessor such as an Intel Pentium processor has control circuitry, either in a dedicated integrated circuit device or as a sub-set of an integrated circuit device, for communicating with and transferring data to and from a disk drive using a given protocol. The I/O device control circuitry is easily accessed by the main or primary system processor at a high-level, thereby insulating the main/primary processor from the underlying details of communicating with the I/O device. One exemplary I/O controller contains an embedded input/output processor (IOP) known as an ARM microprocessor for providing the computational and control functionality within the I/O device integrated circuit controller.
Due to complexities introduced by certain types of protocols such as SAS, memory requirements for embedded controllers or processors such as ARM processors are increasing in order to provide advanced functionality such as error detection and correction, RAID support, increased buffering, etc. However, such increases in memory size come at a cost, as the larger the memory that is included in the device controller, the larger is the corresponding die size of the integrated circuit device. As many of today's computer systems are extremely cost-sensitive, there is a need to provide a flexible memory architecture in a device controller while maintaining a small die size or footprint for the circuitry required to provide such memory functionality. The present invention is directed to such a solution.